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Searched refs:CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE_MASK (Results 1 – 16 of 16) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_amdkfd_gfx_v7.c129 CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE_MASK); in kgd_init_interrupts()
H A Damdgpu_amdkfd_gfx_v8.c124 CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE_MASK); in kgd_init_interrupts()
/linux/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_6_0_sh_mask.h2374 #define CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L macro
H A Dgfx_7_2_sh_mask.h1183 #define CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000 macro
H A Dgfx_8_1_sh_mask.h2035 #define CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000 macro
H A Dgfx_8_0_sh_mask.h1511 #define CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000 macro
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h11011 #define CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE_MASK … macro
H A Dgc_9_1_sh_mask.h12488 #define CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE_MASK … macro
H A Dgc_9_2_1_sh_mask.h12292 #define CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE_MASK … macro
H A Dgc_9_4_2_sh_mask.h2308 #define CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE_MASK … macro
H A Dgc_11_5_0_sh_mask.h12237 #define CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE_MASK … macro
H A Dgc_11_0_0_sh_mask.h15421 #define CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE_MASK … macro
H A Dgc_12_0_0_sh_mask.h11857 #define CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE_MASK … macro
H A Dgc_10_1_0_sh_mask.h17952 #define CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE_MASK … macro
H A Dgc_11_0_3_sh_mask.h17576 #define CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE_MASK … macro
H A Dgc_10_3_0_sh_mask.h16216 #define CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE_MASK global() macro
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