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Searched refs:CP_HQD_SEMA_CMD__RESULT_MASK (Results 1 – 11 of 11) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_7_2_sh_mask.h3413 #define CP_HQD_SEMA_CMD__RESULT_MASK 0x6 macro
H A Dgfx_8_1_sh_mask.h4569 #define CP_HQD_SEMA_CMD__RESULT_MASK 0x6 macro
H A Dgfx_8_0_sh_mask.h4047 #define CP_HQD_SEMA_CMD__RESULT_MASK 0x6 macro
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h13007 #define CP_HQD_SEMA_CMD__RESULT_MASK … macro
H A Dgc_9_1_sh_mask.h14307 #define CP_HQD_SEMA_CMD__RESULT_MASK … macro
H A Dgc_9_2_1_sh_mask.h14172 #define CP_HQD_SEMA_CMD__RESULT_MASK … macro
H A Dgc_9_4_2_sh_mask.h4105 #define CP_HQD_SEMA_CMD__RESULT_MASK … macro
H A Dgc_11_5_0_sh_mask.h14194 #define CP_HQD_SEMA_CMD__RESULT_MASK … macro
H A Dgc_11_0_0_sh_mask.h17500 #define CP_HQD_SEMA_CMD__RESULT_MASK … macro
H A Dgc_10_1_0_sh_mask.h20424 #define CP_HQD_SEMA_CMD__RESULT_MASK … macro
H A Dgc_11_0_3_sh_mask.h19741 #define CP_HQD_SEMA_CMD__RESULT_MASK … macro