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Searched refs:CP_HQD_IQ_TIMER__INTERRUPT_SIZE_MASK (Results 1 – 13 of 13) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_7_2_sh_mask.h3387 #define CP_HQD_IQ_TIMER__INTERRUPT_SIZE_MASK 0x3f0000 macro
H A Dgfx_8_1_sh_mask.h4529 #define CP_HQD_IQ_TIMER__INTERRUPT_SIZE_MASK 0x3f0000 macro
H A Dgfx_8_0_sh_mask.h4007 #define CP_HQD_IQ_TIMER__INTERRUPT_SIZE_MASK 0x3f0000 macro
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h12964 #define CP_HQD_IQ_TIMER__INTERRUPT_SIZE_MASK … macro
H A Dgc_9_1_sh_mask.h14264 #define CP_HQD_IQ_TIMER__INTERRUPT_SIZE_MASK … macro
H A Dgc_9_2_1_sh_mask.h14129 #define CP_HQD_IQ_TIMER__INTERRUPT_SIZE_MASK … macro
H A Dgc_9_4_2_sh_mask.h4062 #define CP_HQD_IQ_TIMER__INTERRUPT_SIZE_MASK … macro
H A Dgc_11_5_0_sh_mask.h14138 #define CP_HQD_IQ_TIMER__INTERRUPT_SIZE_MASK … macro
H A Dgc_11_0_0_sh_mask.h17444 #define CP_HQD_IQ_TIMER__INTERRUPT_SIZE_MASK … macro
H A Dgc_12_0_0_sh_mask.h13341 #define CP_HQD_IQ_TIMER__INTERRUPT_SIZE_MASK … macro
H A Dgc_10_1_0_sh_mask.h20378 #define CP_HQD_IQ_TIMER__INTERRUPT_SIZE_MASK … macro
H A Dgc_11_0_3_sh_mask.h19685 #define CP_HQD_IQ_TIMER__INTERRUPT_SIZE_MASK … macro
H A Dgc_10_3_0_sh_mask.h18531 #define CP_HQD_IQ_TIMER__INTERRUPT_SIZE_MASK global() macro
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