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Searched refs:CP_HQD_IQ_TIMER__CACHE_POLICY__SHIFT (Results 1 – 13 of 13) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_7_2_sh_mask.h3392 #define CP_HQD_IQ_TIMER__CACHE_POLICY__SHIFT 0x18 macro
H A Dgfx_8_1_sh_mask.h4536 #define CP_HQD_IQ_TIMER__CACHE_POLICY__SHIFT 0x18 macro
H A Dgfx_8_0_sh_mask.h4014 #define CP_HQD_IQ_TIMER__CACHE_POLICY__SHIFT 0x18 macro
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h12953 #define CP_HQD_IQ_TIMER__CACHE_POLICY__SHIFT … macro
H A Dgc_9_1_sh_mask.h14253 #define CP_HQD_IQ_TIMER__CACHE_POLICY__SHIFT … macro
H A Dgc_9_2_1_sh_mask.h14118 #define CP_HQD_IQ_TIMER__CACHE_POLICY__SHIFT … macro
H A Dgc_9_4_2_sh_mask.h4051 #define CP_HQD_IQ_TIMER__CACHE_POLICY__SHIFT … macro
H A Dgc_11_5_0_sh_mask.h14126 #define CP_HQD_IQ_TIMER__CACHE_POLICY__SHIFT … macro
H A Dgc_11_0_0_sh_mask.h17432 #define CP_HQD_IQ_TIMER__CACHE_POLICY__SHIFT … macro
H A Dgc_12_0_0_sh_mask.h13330 #define CP_HQD_IQ_TIMER__CACHE_POLICY__SHIFT … macro
H A Dgc_10_1_0_sh_mask.h20366 #define CP_HQD_IQ_TIMER__CACHE_POLICY__SHIFT … macro
H A Dgc_11_0_3_sh_mask.h19673 #define CP_HQD_IQ_TIMER__CACHE_POLICY__SHIFT … macro
H A Dgc_10_3_0_sh_mask.h18519 #define CP_HQD_IQ_TIMER__CACHE_POLICY__SHIFT … macro