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Searched refs:CP_HQD_EOP_CONTROL__EOP_SIZE_MASK (Results 1 – 12 of 12) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_8_1_sh_mask.h4623 #define CP_HQD_EOP_CONTROL__EOP_SIZE_MASK 0x3f macro
H A Dgfx_8_0_sh_mask.h4101 #define CP_HQD_EOP_CONTROL__EOP_SIZE_MASK 0x3f macro
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h13090 #define CP_HQD_EOP_CONTROL__EOP_SIZE_MASK … macro
H A Dgc_9_1_sh_mask.h14390 #define CP_HQD_EOP_CONTROL__EOP_SIZE_MASK … macro
H A Dgc_9_2_1_sh_mask.h14255 #define CP_HQD_EOP_CONTROL__EOP_SIZE_MASK … macro
H A Dgc_9_4_2_sh_mask.h4188 #define CP_HQD_EOP_CONTROL__EOP_SIZE_MASK … macro
H A Dgc_11_5_0_sh_mask.h14326 #define CP_HQD_EOP_CONTROL__EOP_SIZE_MASK … macro
H A Dgc_11_0_0_sh_mask.h17632 #define CP_HQD_EOP_CONTROL__EOP_SIZE_MASK … macro
H A Dgc_12_0_0_sh_mask.h13518 #define CP_HQD_EOP_CONTROL__EOP_SIZE_MASK … macro
H A Dgc_10_1_0_sh_mask.h20512 #define CP_HQD_EOP_CONTROL__EOP_SIZE_MASK … macro
H A Dgc_11_0_3_sh_mask.h19877 #define CP_HQD_EOP_CONTROL__EOP_SIZE_MASK … macro
H A Dgc_10_3_0_sh_mask.h18665 #define CP_HQD_EOP_CONTROL__EOP_SIZE_MASK … macro