Home
last modified time | relevance | path

Searched refs:CP_CE_ROQ_RB_STAT__CEQ_WPTR_PRIMARY_MASK (Results 1 – 8 of 8) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_7_2_sh_mask.h3201 #define CP_CE_ROQ_RB_STAT__CEQ_WPTR_PRIMARY_MASK 0x3ff0000 macro
H A Dgfx_8_1_sh_mask.h4337 #define CP_CE_ROQ_RB_STAT__CEQ_WPTR_PRIMARY_MASK 0x3ff0000 macro
H A Dgfx_8_0_sh_mask.h3815 #define CP_CE_ROQ_RB_STAT__CEQ_WPTR_PRIMARY_MASK 0x3ff0000 macro
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h1318 #define CP_CE_ROQ_RB_STAT__CEQ_WPTR_PRIMARY_MASK … macro
H A Dgc_9_1_sh_mask.h1217 #define CP_CE_ROQ_RB_STAT__CEQ_WPTR_PRIMARY_MASK … macro
H A Dgc_9_2_1_sh_mask.h1184 #define CP_CE_ROQ_RB_STAT__CEQ_WPTR_PRIMARY_MASK … macro
H A Dgc_9_4_2_sh_mask.h1817 #define CP_CE_ROQ_RB_STAT__CEQ_WPTR_PRIMARY_MASK … macro
H A Dgc_10_1_0_sh_mask.h6804 #define CP_CE_ROQ_RB_STAT__CEQ_WPTR_PRIMARY_MASK … macro