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Searched refs:CPT_AF_LFX_CTL (Results 1 – 4 of 4) sorted by relevance

/linux/drivers/crypto/marvell/octeontx2/
H A Dotx2_cptlf.c58 CPT_AF_LFX_CTL(lf->slot), in cptlf_set_pri()
66 CPT_AF_LFX_CTL(lf->slot), in cptlf_set_pri()
79 CPT_AF_LFX_CTL(lf->slot), in cptlf_set_eng_grps_mask()
87 CPT_AF_LFX_CTL(lf->slot), in cptlf_set_eng_grps_mask()
119 CPT_AF_LFX_CTL(lf->slot), in cptlf_set_ctx_ilen()
127 CPT_AF_LFX_CTL(lf->slot), in cptlf_set_ctx_ilen()
/linux/drivers/net/ethernet/marvell/octeontx2/af/
H A Drvu_cpt.c499 rvu_write64(rvu, blkaddr, CPT_AF_LFX_CTL(cptlf), val); in rvu_mbox_handler_cpt_lf_alloc()
567 val = rvu_read64(rvu, blkaddr, CPT_AF_LFX_CTL(cptlf)); in cpt_inline_ipsec_cfg_inbound()
587 rvu_write64(rvu, blkaddr, CPT_AF_LFX_CTL(cptlf), val); in cpt_inline_ipsec_cfg_inbound()
622 val = rvu_read64(rvu, blkaddr, CPT_AF_LFX_CTL(cptlf)); in cpt_inline_ipsec_cfg_outbound()
640 rvu_write64(rvu, blkaddr, CPT_AF_LFX_CTL(cptlf), val); in cpt_inline_ipsec_cfg_outbound()
651 val = rvu_read64(rvu, blkaddr, CPT_AF_LFX_CTL(cptlf)); in cpt_inline_ipsec_cfg_outbound()
653 rvu_write64(rvu, blkaddr, CPT_AF_LFX_CTL(cptlf), val); in cpt_inline_ipsec_cfg_outbound()
709 if ((offset & 0xFF000) == CPT_AF_LFX_CTL(0) || in validate_and_update_reg_offset()
969 ctl = rvu_read64(rvu, blkaddr, CPT_AF_LFX_CTL(cptlf)); in rvu_mbox_handler_cpt_lf_reset()
977 rvu_write64(rvu, blkaddr, CPT_AF_LFX_CTL(cptlf), ctl); in rvu_mbox_handler_cpt_lf_reset()
H A Drvu_reg.h510 #define CPT_AF_LFX_CTL(a) (0x27000ull | (u64)(a) << 3) macro
H A Drvu_debugfs.c3736 reg = rvu_read64(rvu, blkaddr, CPT_AF_LFX_CTL(lf)); in rvu_dbg_cpt_lfs_info_display()