Searched refs:CPOL (Results 1 – 4 of 4) sorted by relevance
412 new_polarity = (asd->csr & SPI_BIT(CPOL)) != 0; in cs_activate()425 u32 cpol = (spi->mode & SPI_CPOL) ? SPI_BIT(CPOL) : 0; in cs_activate()432 if ((csr ^ cpol) & SPI_BIT(CPOL)) in cs_activate()434 csr ^ SPI_BIT(CPOL)); in cs_activate()1284 csr |= SPI_BIT(CPOL); in atmel_spi_setup()
100 #define CPOL BIT(15) macro895 conf |= CPOL; in aml_spi_settings()900 CPHA | CPOL | RXADJ | in aml_spi_settings()
30 #define CPOL BIT(2) macro365 writel((spi_slv->mode & SPI_CPOL) ? CPOL : 0, se->base + SE_SPI_CPOL); in setup_fifo_params()
100 - CPOL indicates the initial clock polarity. CPOL=0 means the102 the second (trailing) edge is falling. CPOL=1 means the clock113 but their timing diagrams will make the CPOL and CPHA modes clear.115 In the SPI mode number, CPOL is the high order bit and CPHA is the117 starting low (CPOL=0) and data stabilized for sampling during the622 each other. For example, in SPI mode 0 (CPOL=0, CPHA=0) the bus lines may behave