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Searched refs:CPLL (Results 1 – 3 of 3) sorted by relevance

/linux/arch/arm/boot/dts/samsung/
H A Dexynos5422-odroid-core.dtsi71 /* derived from 666MHz CPLL */
89 /* derived from 666MHz CPLL */
116 /* derived from 666MHz CPLL */
155 /* derived from 666MHz CPLL */
164 /* derived from 666MHz CPLL */
221 /* derived from 666MHz CPLL */
281 /* derived from 666MHz CPLL */
/linux/include/dt-bindings/clock/
H A Dxlnx-versal-clk.h35 #define CPLL 26 macro
/linux/arch/arm64/boot/dts/rockchip/
H A Drk3328.dtsi824 * CPLL should run at 1200, but that is to high for