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Searched refs:CPG_PLL_MON (Results 1 – 1 of 1) sorted by relevance

/linux/drivers/clk/renesas/
H A Drzv2h-cpg.c65 #define CPG_PLL_MON(x) ((x) + 0x010) macro
601 ret = readl_poll_timeout_atomic(priv->base + CPG_PLL_MON(offset), in rzv2h_cpg_pll_set_rate()
629 ret = readl_poll_timeout_atomic(priv->base + CPG_PLL_MON(offset), in rzv2h_cpg_pll_set_rate()
656 u32 val = readl(priv->base + CPG_PLL_MON(pll_clk->pll.offset)); in rzv2h_cpg_pll_clk_is_enabled()
677 mon_offset = CPG_PLL_MON(pll.offset); in rzv2h_cpg_pll_clk_enable()