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Searched refs:CPG_PLL_CLK1_OFFSET (Results 1 – 1 of 1) sorted by relevance

/linux/drivers/clk/renesas/
H A Drzg2l-cpg.c64 #define CPG_PLL_CLK1_OFFSET(x) (CPG_PLL_STBY_OFFSET(x) + 0x4) macro
1089 val1 = readl(priv->base + CPG_PLL_CLK1_OFFSET(pll_clk->conf)); in rzg2l_cpg_pll_clk_recalc_rate()
1117 val = readl(priv->base + CPG_PLL_CLK1_OFFSET(pll_clk->conf)); in rzg3s_cpg_pll_clk_recalc_rate()