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Searched refs:CPG_PLL1_SETTING_OFFSET (Results 1 – 1 of 1) sorted by relevance

/linux/drivers/clk/renesas/
H A Drzg2l-cpg.c60 #define CPG_PLL1_SETTING_OFFSET(conf) FIELD_GET(GENMASK(11, 0), (conf)) macro
1110 setting = CPG_PLL1_SETTING_OFFSET(pll_clk->conf); in rzg3s_cpg_pll_clk_recalc_rate()