Searched refs:CPG_PLL0CR (Results 1 – 4 of 4) sorted by relevance
27 #define CPG_PLL0CR 0xd8 macro92 u32 value = readl(base + CPG_PLL0CR); in r8a73a4_cpg_register_clock()
29 #define CPG_PLL0CR 0xd8 macro94 enable_reg += CPG_PLL0CR; in sh73a0_cpg_register_clock()
24 #define CPG_PLL0CR 0x00d8 macro310 u32 pll0cr = readl(base + CPG_PLL0CR); in rcar_gen2_cpg_clk_register()
33 #define CPG_PLL0CR 0x00d8 /* PLLn Control Registers */ macro369 base, 2, CPG_PLL0CR, 0); in rcar_gen3_cpg_clk_register()