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Searched refs:CONTROL_REG (Results 1 – 4 of 4) sorted by relevance

/linux/drivers/rtc/
H A Drtc-mpfs.c22 #define CONTROL_REG 0x00 macro
65 ctrl = readl(rtcdev->base + CONTROL_REG); in mpfs_rtc_start()
68 writel(ctrl, rtcdev->base + CONTROL_REG); in mpfs_rtc_start()
73 u32 val = readl(rtcdev->base + CONTROL_REG); in mpfs_rtc_clear_irq()
77 writel(val, rtcdev->base + CONTROL_REG); in mpfs_rtc_clear_irq()
83 (void)readl(rtcdev->base + CONTROL_REG); in mpfs_rtc_clear_irq()
110 ctrl = readl(rtcdev->base + CONTROL_REG); in mpfs_rtc_settime()
113 writel(ctrl, rtcdev->base + CONTROL_REG); in mpfs_rtc_settime()
116 false, rtcdev->base + CONTROL_REG); in mpfs_rtc_settime()
148 ctrl = readl(rtcdev->base + CONTROL_REG); in mpfs_rtc_setalarm()
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/linux/drivers/char/hw_random/
H A Dxiphera-trng.c13 #define CONTROL_REG 0x00000000 macro
48 writel(HOST_TO_TRNG_READ, trng->mem + CONTROL_REG); in xiphera_trng_read()
49 writel(HOST_TO_TRNG_ENABLE, trng->mem + CONTROL_REG); in xiphera_trng_read()
78 writel(HOST_TO_TRNG_RESET, trng->mem + CONTROL_REG); in xiphera_trng_probe()
97 writel(HOST_TO_TRNG_RELEASE_RESET, trng->mem + CONTROL_REG); in xiphera_trng_probe()
98 writel(HOST_TO_TRNG_ENABLE, trng->mem + CONTROL_REG); in xiphera_trng_probe()
99 writel(HOST_TO_TRNG_ZEROIZE, trng->mem + CONTROL_REG); in xiphera_trng_probe()
112 writel(HOST_TO_TRNG_ACK_ZEROIZE, trng->mem + CONTROL_REG); in xiphera_trng_probe()
/linux/drivers/net/ethernet/qlogic/
H A Dqla3xxx.h697 CONTROL_REG = 0, enumerator
H A Dqla3xxx.c1325 ql_mii_write_reg_ex(qdev, CONTROL_REG, PHY_CTRL_SOFT_RESET, in ql_phy_reset_ex()
1395 ql_mii_read_reg_ex(qdev, CONTROL_REG, &reg, PHYAddr[qdev->mac_index]); in ql_phy_start_neg_ex()
1397 ql_mii_write_reg_ex(qdev, CONTROL_REG, in ql_phy_start_neg_ex()