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Searched refs:CLK_VPP1_VPP0_DL_ASYNC (Results 1 – 4 of 4) sorted by relevance

/linux/drivers/clk/mediatek/
H A Dclk-mt8195-vpp1.c82 GATE_VPP1_1(CLK_VPP1_VPP0_DL_ASYNC, "vpp1_vpp0_dl_async", "top_vpp", 16),
H A Dclk-mt8188-vpp1.c76 GATE_VPP1_1(CLK_VPP1_VPP0_DL_ASYNC, "vpp1_vpp0_dl_async", "top_vpp", 10),
/linux/include/dt-bindings/clock/
H A Dmediatek,mt8188-clk.h481 #define CLK_VPP1_VPP0_DL_ASYNC 41 macro
H A Dmt8195-clk.h592 #define CLK_VPP1_VPP0_DL_ASYNC 48 macro