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Searched refs:CLK_VPP0_WARP1_RELAY (Results 1 – 4 of 4) sorted by relevance

/linux/drivers/clk/mediatek/
H A Dclk-mt8195-vpp0.c85 GATE_VPP0_2(CLK_VPP0_WARP1_RELAY, "vpp0_warp1_relay", "top_wpe_vpp", 2),
H A Dclk-mt8188-vpp0.c90 GATE_VPP0_2(CLK_VPP0_WARP1_RELAY, "vpp0_warp1_relay", "top_wpe_vpp", 2),
/linux/include/dt-bindings/clock/
H A Dmediatek,mt8188-clk.h402 #define CLK_VPP0_WARP1_RELAY 43 macro
H A Dmt8195-clk.h473 #define CLK_VPP0_WARP1_RELAY 40 macro