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Searched refs:CLK_VPP0_WARP0_ASYNC_TX (Results 1 – 4 of 4) sorted by relevance

/linux/drivers/clk/mediatek/
H A Dclk-mt8195-vpp0.c46 GATE_VPP0_0(CLK_VPP0_WARP0_ASYNC_TX, "vpp0_warp0_async_tx", "top_vpp", 10),
H A Dclk-mt8188-vpp0.c47 GATE_VPP0_0(CLK_VPP0_WARP0_ASYNC_TX, "vpp0_warp0_async_tx", "top_vpp", 10),
/linux/include/dt-bindings/clock/
H A Dmediatek,mt8188-clk.h363 #define CLK_VPP0_WARP0_ASYNC_TX 4 macro
H A Dmt8195-clk.h437 #define CLK_VPP0_WARP0_ASYNC_TX 4 macro