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Searched refs:CLK_TOP_VENC_SEL (Results 1 – 14 of 14) sorted by relevance

/linux/include/dt-bindings/clock/
H A Dmt8135-clk.h86 #define CLK_TOP_VENC_SEL 75 macro
H A Dmediatek,mt6795-clk.h96 #define CLK_TOP_VENC_SEL 85 macro
H A Dmt8173-clk.h98 #define CLK_TOP_VENC_SEL 88 macro
H A Dmt2712-clk.h135 #define CLK_TOP_VENC_SEL 104 macro
H A Dmt8192-clk.h63 #define CLK_TOP_VENC_SEL 51 macro
/linux/drivers/clk/mediatek/
H A Dclk-mt6795-topckgen.c462 TOP_MUX_GATE(CLK_TOP_VENC_SEL, "venc_sel", venc_parents, 0x50, 16, 4, 23, 0),
H A Dclk-mt8173-topckgen.c541 MUX_GATE(CLK_TOP_VENC_SEL, "venc_sel", venc_parents, 0x0050, 16, 4, 23),
H A Dclk-mt8135.c373 MUX_GATE(CLK_TOP_VENC_SEL, "venc_sel", venc_parents, 0x0150, 8, 3, 15),
H A Dclk-mt2712.c652 MUX_GATE(CLK_TOP_VENC_SEL, "venc_sel", venc_parents, 0x050, 16, 4, 23),
H A Dclk-mt8192.c667 MUX_GATE_CLR_SET_UPD(CLK_TOP_VENC_SEL, "venc_sel",
/linux/arch/arm64/boot/dts/mediatek/
H A Dmt8173.dtsi466 <&topckgen CLK_TOP_VENC_SEL>;
1476 clocks = <&topckgen CLK_TOP_VENC_SEL>;
1478 assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>;
H A Dmt2712e.dtsi287 <&topckgen CLK_TOP_VENC_SEL>,
H A Dmt6795.dtsi311 <&topckgen CLK_TOP_VENC_SEL>;
H A Dmt8192.dtsi628 clocks = <&topckgen CLK_TOP_VENC_SEL>,
1827 assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>;