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Searched refs:CLK_TOP_VDEC_SEL (Results 1 – 15 of 15) sorted by relevance

/linux/include/dt-bindings/clock/
H A Dmt8135-clk.h93 #define CLK_TOP_VDEC_SEL 82 macro
H A Dmediatek,mt6795-clk.h95 #define CLK_TOP_VDEC_SEL 84 macro
H A Dmt8173-clk.h97 #define CLK_TOP_VDEC_SEL 87 macro
H A Dmt2712-clk.h134 #define CLK_TOP_VDEC_SEL 103 macro
H A Dmt2701-clk.h93 #define CLK_TOP_VDEC_SEL 82 macro
H A Dmt8192-clk.h64 #define CLK_TOP_VDEC_SEL 52 macro
/linux/drivers/clk/mediatek/
H A Dclk-mt6795-topckgen.c461 TOP_MUX_GATE(CLK_TOP_VDEC_SEL, "vdec_sel", vdec_parents, 0x50, 8, 4, 15, 0),
H A Dclk-mt8173-topckgen.c540 MUX_GATE(CLK_TOP_VDEC_SEL, "vdec_sel", vdec_parents, 0x0050, 8, 4, 15),
H A Dclk-mt8135.c382 MUX_GATE(CLK_TOP_VDEC_SEL, "vdec_sel", vdec_parents, 0x015c, 8, 4, 15),
H A Dclk-mt2712.c651 MUX_GATE(CLK_TOP_VDEC_SEL, "vdec_sel", vdec_parents, 0x050, 8, 4, 15),
H A Dclk-mt8192.c669 MUX_GATE_CLR_SET_UPD(CLK_TOP_VDEC_SEL, "vdec_sel",
H A Dclk-mt2701.c498 MUX_GATE(CLK_TOP_VDEC_SEL, "vdec_sel", vdec_parents,
/linux/arch/arm64/boot/dts/mediatek/
H A Dmt8192.dtsi637 clocks = <&topckgen CLK_TOP_VDEC_SEL>,
1719 clocks = <&topckgen CLK_TOP_VDEC_SEL>,
1725 assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>;
1745 clocks = <&topckgen CLK_TOP_VDEC_SEL>,
1751 assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>;
H A Dmt8173.dtsi1410 <&topckgen CLK_TOP_VDEC_SEL>,
1425 <&topckgen CLK_TOP_VDEC_SEL>,
H A Dmt2712e.dtsi290 <&topckgen CLK_TOP_VDEC_SEL>;