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Searched refs:CLK_TOP_USB20_SEL (Results 1 – 12 of 12) sorted by relevance

/linux/include/dt-bindings/clock/
H A Dmediatek,mt6735-topckgen.h59 #define CLK_TOP_USB20_SEL 51 macro
H A Dmt8135-clk.h85 #define CLK_TOP_USB20_SEL 74 macro
H A Dmediatek,mt6795-clk.h101 #define CLK_TOP_USB20_SEL 90 macro
H A Dmt8173-clk.h103 #define CLK_TOP_USB20_SEL 93 macro
H A Dmt2712-clk.h140 #define CLK_TOP_USB20_SEL 109 macro
H A Dmt2701-clk.h96 #define CLK_TOP_USB20_SEL 85 macro
/linux/drivers/clk/mediatek/
H A Dclk-mt6735-topckgen.c345 …MUX_GATE_CLR_SET_UPD(CLK_TOP_USB20_SEL, "usb20_sel", usb20_sel_parents, CLK_CFG_2, CLK_CFG_2_SET, …
H A Dclk-mt6795-topckgen.c468 TOP_MUX_GATE(CLK_TOP_USB20_SEL, "usb20_sel", usb20_parents, 0x60, 24, 2, 31, 0),
H A Dclk-mt8173-topckgen.c547 MUX_GATE(CLK_TOP_USB20_SEL, "usb20_sel", usb20_parents, 0x0060, 24, 2, 31),
H A Dclk-mt8135.c371 MUX_GATE(CLK_TOP_USB20_SEL, "usb20_sel", usb20_parents, 0x014c, 0, 2, 7),
H A Dclk-mt2712.c658 MUX_GATE(CLK_TOP_USB20_SEL, "usb20_sel", usb20_parents, 0x060, 24, 2, 31),
H A Dclk-mt2701.c509 MUX_GATE(CLK_TOP_USB20_SEL, "usb20_sel", usb20_parents,