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Searched refs:CLK_TOP_SYSAXI_SEL (Results 1 – 6 of 6) sorted by relevance

/linux/include/dt-bindings/clock/
H A Dmt7986-clk.h62 #define CLK_TOP_SYSAXI_SEL 39 macro
H A Dmediatek,mt7981-clk.h102 #define CLK_TOP_SYSAXI_SEL 89 macro
H A Dmediatek,mt7988-clk.h101 #define CLK_TOP_SYSAXI_SEL 73 macro
/linux/drivers/clk/mediatek/
H A Dclk-mt7986-topckgen.c212 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SYSAXI_SEL, "sysaxi_sel",
H A Dclk-mt7981-topckgen.c330 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SYSAXI_SEL, "sysaxi_sel",
H A Dclk-mt7988-topckgen.c204 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SYSAXI_SEL, "sysaxi_sel", axi_infra_parents, 0x0a0,