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Searched refs:CLK_TOP_PEXTP_TL_SEL (Results 1 – 6 of 6) sorted by relevance

/linux/include/dt-bindings/clock/
H A Dmt7986-clk.h56 #define CLK_TOP_PEXTP_TL_SEL 33 macro
H A Dmediatek,mt7981-clk.h96 #define CLK_TOP_PEXTP_TL_SEL 83 macro
H A Dmediatek,mt7988-clk.h77 #define CLK_TOP_PEXTP_TL_SEL 49 macro
/linux/drivers/clk/mediatek/
H A Dclk-mt7986-topckgen.c190 MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_TL_SEL, "pextp_tl_ck_sel",
H A Dclk-mt7981-topckgen.c307 MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_TL_SEL, "pextp_tl_ck_sel",
H A Dclk-mt7988-topckgen.c149 MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_TL_SEL, "pextp_tl_sel", pextp_tl_ck_parents, 0x040,