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Searched refs:CLK_TOP_NFIECC_SEL (Results 1 – 7 of 7) sorted by relevance

/linux/include/dt-bindings/clock/
H A Dmt8516-clk.h195 #define CLK_TOP_NFIECC_SEL 163 macro
H A Dmediatek,mt8365-clk.h107 #define CLK_TOP_NFIECC_SEL 97 macro
H A Dmt2712-clk.h161 #define CLK_TOP_NFIECC_SEL 130 macro
/linux/drivers/clk/mediatek/
H A Dclk-mt8516.c435 MUX(CLK_TOP_NFIECC_SEL, "nfiecc_sel", nfiecc_parents,
H A Dclk-mt8167.c624 MUX(CLK_TOP_NFIECC_SEL, "nfiecc_sel", nfiecc_parents,
H A Dclk-mt2712.c695 MUX_GATE(CLK_TOP_NFIECC_SEL, "nfiecc_sel", nfiecc_parents, 0x0c0, 0, 3, 7),
H A Dclk-mt8365.c510 MUX_GATE_CLR_SET_UPD(CLK_TOP_NFIECC_SEL, "nfiecc_sel", nfiecc_parents,