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Searched refs:CLK_TOP_NFI1X_SEL (Results 1 – 6 of 6) sorted by relevance

/linux/include/dt-bindings/clock/
H A Dmt7986-clk.h49 #define CLK_TOP_NFI1X_SEL 26 macro
H A Dmediatek,mt7981-clk.h89 #define CLK_TOP_NFI1X_SEL 76 macro
H A Dmediatek,mt7988-clk.h72 #define CLK_TOP_NFI1X_SEL 44 macro
/linux/drivers/clk/mediatek/
H A Dclk-mt7986-topckgen.c175 MUX_GATE_CLR_SET_UPD(CLK_TOP_NFI1X_SEL, "nfi1x_sel", nfi1x_parents,
H A Dclk-mt7981-topckgen.c292 MUX_GATE_CLR_SET_UPD(CLK_TOP_NFI1X_SEL, "nfi1x_sel", nfi1x_parents,
H A Dclk-mt7988-topckgen.c138 MUX_GATE_CLR_SET_UPD(CLK_TOP_NFI1X_SEL, "nfi1x_sel", nfi1x_parents, 0x030, 0x034, 0x038, 16,