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Searched refs:CLK_TOP_NETSYS_GSW_SEL (Results 1 – 2 of 2) sorted by relevance

/linux/include/dt-bindings/clock/
H A Dmediatek,mt7988-clk.h61 #define CLK_TOP_NETSYS_GSW_SEL 33 macro
/linux/drivers/clk/mediatek/
H A Dclk-mt7988-topckgen.c113 MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_GSW_SEL, "netsys_gsw_sel", netsys_gsw_parents, 0x000,