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Searched refs:CLK_TOP_MSDC30_2_SEL (Results 1 – 14 of 14) sorted by relevance

/linux/include/dt-bindings/clock/
H A Dmediatek,mt6735-topckgen.h63 #define CLK_TOP_MSDC30_2_SEL 55 macro
H A Dmt8135-clk.h82 #define CLK_TOP_MSDC30_2_SEL 71 macro
H A Dmediatek,mt6795-clk.h106 #define CLK_TOP_MSDC30_2_SEL 95 macro
H A Dmt8173-clk.h108 #define CLK_TOP_MSDC30_2_SEL 98 macro
H A Dmt2712-clk.h145 #define CLK_TOP_MSDC30_2_SEL 114 macro
H A Dmt2701-clk.h101 #define CLK_TOP_MSDC30_2_SEL 90 macro
H A Dmt8192-clk.h38 #define CLK_TOP_MSDC30_2_SEL 26 macro
/linux/drivers/clk/mediatek/
H A Dclk-mt6735-topckgen.c349 …MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC30_2_SEL, "msdc30_2_sel", msdc30_1_2_sel_parents, CLK_CFG_3, CLK_…
H A Dclk-mt6795-topckgen.c476 TOP_MUX_GATE(CLK_TOP_MSDC30_2_SEL, "msdc30_2_sel", msdc30_2_parents, 0x80, 0, 3, 7, 0),
H A Dclk-mt8173-topckgen.c557 MUX_GATE_FLAGS(CLK_TOP_MSDC30_2_SEL, "msdc30_2_sel", msdc30_2_parents,
H A Dclk-mt8135.c367 MUX_GATE(CLK_TOP_MSDC30_2_SEL, "msdc30_2_sel", msdc30_parents, 0x0148, 8, 3, 15),
H A Dclk-mt2712.c668 MUX_GATE(CLK_TOP_MSDC30_2_SEL, "msdc30_2_sel", msdc30_1_parents,
H A Dclk-mt8192.c610 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC30_2_SEL, "msdc30_2_sel",
H A Dclk-mt2701.c516 MUX_GATE(CLK_TOP_MSDC30_2_SEL, "msdc30_2_sel", msdc30_parents,