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Searched refs:CLK_TOP_MSDC30_0_SEL (Results 1 – 10 of 10) sorted by relevance

/linux/include/dt-bindings/clock/
H A Dmediatek,mt6735-topckgen.h61 #define CLK_TOP_MSDC30_0_SEL 53 macro
H A Dmt8135-clk.h97 #define CLK_TOP_MSDC30_0_SEL 86 macro
H A Dmt7629-clk.h95 #define CLK_TOP_MSDC30_0_SEL 85 macro
H A Dmt7622-clk.h80 #define CLK_TOP_MSDC30_0_SEL 68 macro
H A Dmt2701-clk.h95 #define CLK_TOP_MSDC30_0_SEL 84 macro
/linux/drivers/clk/mediatek/
H A Dclk-mt6735-topckgen.c347 …MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC30_0_SEL, "msdc30_0_sel", msdc30_0_sel_parents, CLK_CFG_3, CLK_CF…
H A Dclk-mt7622.c415 MUX_GATE(CLK_TOP_MSDC30_0_SEL, "msdc30_0_sel", msdc30_0_parents,
H A Dclk-mt8135.c388 MUX_GATE(CLK_TOP_MSDC30_0_SEL, "msdc30_0_sel", msdc30_parents, 0x0164, 8, 3, 15),
H A Dclk-mt2701.c510 MUX_GATE(CLK_TOP_MSDC30_0_SEL, "msdc30_0_sel", msdc30_parents,
/linux/arch/arm64/boot/dts/mediatek/
H A Dmt7622-bananapi-bpi-r64.dts242 assigned-clocks = <&topckgen CLK_TOP_MSDC30_0_SEL>;