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Searched refs:CLK_TOP_MFG_PLL_SEL (Results 1 – 2 of 2) sorted by relevance

/linux/drivers/clk/mediatek/
H A Dclk-mt8192.c581 MUX_CLR_SET(CLK_TOP_MFG_PLL_SEL, "mfg_pll_sel", mfg_pll_parents,
976 if (top_mtk_muxes[i].id == CLK_TOP_MFG_PLL_SEL) in clk_mt8192_reg_mfg_mux_notifier()
1011 .mfg_clk_idx = CLK_TOP_MFG_PLL_SEL,
/linux/include/dt-bindings/clock/
H A Dmt8192-clk.h26 #define CLK_TOP_MFG_PLL_SEL 14 macro