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Searched refs:CLK_TOP_IRTX_SEL (Results 1 – 5 of 5) sorted by relevance

/linux/include/dt-bindings/clock/
H A Dmediatek,mt6735-topckgen.h76 #define CLK_TOP_IRTX_SEL 68 macro
H A Dmt7629-clk.h110 #define CLK_TOP_IRTX_SEL 100 macro
H A Dmt7622-clk.h95 #define CLK_TOP_IRTX_SEL 83 macro
/linux/drivers/clk/mediatek/
H A Dclk-mt6735-topckgen.c362 …MUX_GATE_CLR_SET_UPD(CLK_TOP_IRTX_SEL, "irtx_sel", irtx_sel_parents, CLK_CFG_6, CLK_CFG_6_SET, CLK…
H A Dclk-mt7622.c452 MUX_GATE(CLK_TOP_IRTX_SEL, "irtx_sel", f10m_ref_parents,