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Searched refs:CLK_TOP_IRDA_SEL (Results 1 – 10 of 10) sorted by relevance

/linux/include/dt-bindings/clock/
H A Dmediatek,mt6735-topckgen.h75 #define CLK_TOP_IRDA_SEL 67 macro
H A Dmt8135-clk.h76 #define CLK_TOP_IRDA_SEL 65 macro
H A Dmediatek,mt6795-clk.h114 #define CLK_TOP_IRDA_SEL 103 macro
H A Dmt8173-clk.h117 #define CLK_TOP_IRDA_SEL 107 macro
H A Dmt2712-clk.h154 #define CLK_TOP_IRDA_SEL 123 macro
/linux/drivers/clk/mediatek/
H A Dclk-mt6735-topckgen.c361 …MUX_GATE_CLR_SET_UPD(CLK_TOP_IRDA_SEL, "irda_sel", irda_sel_parents, CLK_CFG_6, CLK_CFG_6_SET, CLK…
H A Dclk-mt6795-topckgen.c491 TOP_MUX_GATE(CLK_TOP_IRDA_SEL, "irda_sel", irda_parents, 0xa0, 8, 2, 15, 0),
H A Dclk-mt8173-topckgen.c579 MUX_GATE(CLK_TOP_IRDA_SEL, "irda_sel", irda_parents, 0x00a0, 8, 2, 15),
H A Dclk-mt8135.c358 MUX_GATE(CLK_TOP_IRDA_SEL, "irda_sel", irda_parents, 0x0140, 24, 2, 31),
H A Dclk-mt2712.c684 MUX_GATE(CLK_TOP_IRDA_SEL, "irda_sel", irda_parents, 0x0a0, 8, 2, 15),