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Searched refs:CLK_TOP_EIP197_SEL (Results 1 – 2 of 2) sorted by relevance

/linux/include/dt-bindings/clock/
H A Dmediatek,mt7988-clk.h65 #define CLK_TOP_EIP197_SEL 37 macro
/linux/drivers/clk/mediatek/
H A Dclk-mt7988-topckgen.c122 MUX_GATE_CLR_SET_UPD(CLK_TOP_EIP197_SEL, "eip197_sel", eip197_parents, 0x010, 0x014, 0x018,