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Searched refs:CLK_TOP_DISP_PWM_SEL (Results 1 – 6 of 6) sorted by relevance

/linux/include/dt-bindings/clock/
H A Dmt6765-clk.h150 #define CLK_TOP_DISP_PWM_SEL 115 macro
H A Dmediatek,mt8365-clk.h93 #define CLK_TOP_DISP_PWM_SEL 83 macro
H A Dmt8192-clk.h45 #define CLK_TOP_DISP_PWM_SEL 33 macro
/linux/drivers/clk/mediatek/
H A Dclk-mt8365.c471 MUX_GATE_CLR_SET_UPD(CLK_TOP_DISP_PWM_SEL, "disp_pwm_sel",
H A Dclk-mt8192.c626 MUX_GATE_CLR_SET_UPD(CLK_TOP_DISP_PWM_SEL, "disp_pwm_sel",
/linux/arch/arm64/boot/dts/mediatek/
H A Dmt8365.dtsi671 clocks = <&topckgen CLK_TOP_DISP_PWM_SEL>, <&infracfg CLK_IFR_DISP_PWM>;