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Searched refs:CLK_TOP_DDRPHY_SEL (Results 1 – 2 of 2) sorted by relevance

/linux/include/dt-bindings/clock/
H A Dmediatek,mt6735-topckgen.h51 #define CLK_TOP_DDRPHY_SEL 43 macro
/linux/drivers/clk/mediatek/
H A Dclk-mt6735-topckgen.c337 …MUX_CLR_SET_UPD(CLK_TOP_DDRPHY_SEL, "ddrphycfg_sel", ddrphycfg_parents, CLK_CFG_0, CLK_CFG_0_SET, …