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Searched refs:CLK_TOP_CAMTG_SEL (Results 1 – 18 of 18) sorted by relevance

/linux/include/dt-bindings/clock/
H A Dmediatek,mt6735-topckgen.h56 #define CLK_TOP_CAMTG_SEL 48 macro
H A Dmt8135-clk.h90 #define CLK_TOP_CAMTG_SEL 79 macro
H A Dmediatek,mt6795-clk.h98 #define CLK_TOP_CAMTG_SEL 87 macro
H A Dmt8173-clk.h100 #define CLK_TOP_CAMTG_SEL 90 macro
H A Dmt6765-clk.h137 #define CLK_TOP_CAMTG_SEL 102 macro
H A Dmediatek,mt8365-clk.h77 #define CLK_TOP_CAMTG_SEL 67 macro
H A Dmt2712-clk.h137 #define CLK_TOP_CAMTG_SEL 106 macro
H A Dmt2701-clk.h91 #define CLK_TOP_CAMTG_SEL 80 macro
H A Dmt8192-clk.h27 #define CLK_TOP_CAMTG_SEL 15 macro
/linux/drivers/clk/mediatek/
H A Dclk-mt6735-topckgen.c342 …MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG_SEL, "camtg_sel", camtg_sel_parents, CLK_CFG_1, CLK_CFG_1_SET, …
H A Dclk-mt6795-topckgen.c465 TOP_MUX_GATE(CLK_TOP_CAMTG_SEL, "camtg_sel", camtg_parents, 0x60, 0, 3, 7, 0),
H A Dclk-mt8173-topckgen.c544 MUX_GATE(CLK_TOP_CAMTG_SEL, "camtg_sel", camtg_parents, 0x0060, 0, 3, 7),
H A Dclk-mt8135.c378 MUX_GATE(CLK_TOP_CAMTG_SEL, "camtg_sel", camtg_parents, 0x0158, 8, 3, 15),
H A Dclk-mt2712.c655 MUX_GATE(CLK_TOP_CAMTG_SEL, "camtg_sel", camtg_parents, 0x060, 0, 4, 7),
H A Dclk-mt8365.c424 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG_SEL, "camtg_sel", camtg_parents,
H A Dclk-mt8192.c584 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG_SEL, "camtg_sel",
H A Dclk-mt6765.c389 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG_SEL, "camtg_sel",
H A Dclk-mt2701.c502 MUX_GATE(CLK_TOP_CAMTG_SEL, "camtg_sel", camtg_parents,