| /linux/include/dt-bindings/clock/ |
| H A D | mediatek,mt6735-topckgen.h | 49 #define CLK_TOP_AXI_SEL 41 macro
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| H A D | mt8135-clk.h | 73 #define CLK_TOP_AXI_SEL 62 macro
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| H A D | mt7629-clk.h | 83 #define CLK_TOP_AXI_SEL 73 macro
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| H A D | mt7622-clk.h | 68 #define CLK_TOP_AXI_SEL 56 macro
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| H A D | mediatek,mt6795-clk.h | 90 #define CLK_TOP_AXI_SEL 79 macro
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| H A D | mt8173-clk.h | 92 #define CLK_TOP_AXI_SEL 82 macro
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| H A D | mt6765-clk.h | 131 #define CLK_TOP_AXI_SEL 96 macro
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| H A D | mediatek,mt8365-clk.h | 71 #define CLK_TOP_AXI_SEL 61 macro
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| H A D | mt2712-clk.h | 130 #define CLK_TOP_AXI_SEL 99 macro
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| H A D | mt2701-clk.h | 90 #define CLK_TOP_AXI_SEL 79 macro
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| H A D | mt8192-clk.h | 12 #define CLK_TOP_AXI_SEL 0 macro
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| /linux/arch/arm/boot/dts/mediatek/ |
| H A D | mt7629.dtsi | 267 assigned-clocks = <&topckgen CLK_TOP_AXI_SEL>;
319 assigned-clocks = <&topckgen CLK_TOP_AXI_SEL>,
388 <&topckgen CLK_TOP_AXI_SEL>,
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| /linux/drivers/clk/mediatek/ |
| H A D | clk-mt6735-topckgen.c | 335 …MUX_CLR_SET_UPD(CLK_TOP_AXI_SEL, "axi_sel", axi_sel_parents, CLK_CFG_0, CLK_CFG_0_SET, CLK_CFG_0_C…
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| H A D | clk-mt6795-topckgen.c | 452 TOP_MUX_GATE_NOSR(CLK_TOP_AXI_SEL, "axi_sel", axi_parents,
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| H A D | clk-mt8173-topckgen.c | 531 MUX(CLK_TOP_AXI_SEL, "axi_sel", axi_parents, 0x0040, 0, 3),
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| H A D | clk-mt8135.c | 354 MUX_GATE(CLK_TOP_AXI_SEL, "axi_sel", axi_parents,
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| H A D | clk-mt7622.c | 386 MUX_GATE_FLAGS(CLK_TOP_AXI_SEL, "axi_sel", axi_parents,
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| H A D | clk-mt2712.c | 644 MUX_GATE_FLAGS(CLK_TOP_AXI_SEL, "axi_sel", axi_parents, 0x040, 0, 3,
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| H A D | clk-mt8365.c | 410 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_AXI_SEL, "axi_sel", axi_parents,
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| H A D | clk-mt8192.c | 548 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_AXI_SEL, "axi_sel",
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| /linux/arch/arm64/boot/dts/mediatek/ |
| H A D | mt7622.dtsi | 260 <&topckgen CLK_TOP_AXI_SEL>;
720 <&topckgen CLK_TOP_AXI_SEL>;
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| H A D | mt2712e.dtsi | 780 <&topckgen CLK_TOP_AXI_SEL>,
791 <&topckgen CLK_TOP_AXI_SEL>,
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