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Searched refs:CLK_TOP_AUD_L_SEL (Results 1 – 6 of 6) sorted by relevance

/linux/include/dt-bindings/clock/
H A Dmt7986-clk.h78 #define CLK_TOP_AUD_L_SEL 55 macro
H A Dmediatek,mt7981-clk.h116 #define CLK_TOP_AUD_L_SEL 103 macro
H A Dmediatek,mt7988-clk.h89 #define CLK_TOP_AUD_L_SEL 61 macro
/linux/drivers/clk/mediatek/
H A Dclk-mt7986-topckgen.c265 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_L_SEL, "aud_l_sel", aud_l_parents,
H A Dclk-mt7981-topckgen.c373 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_L_SEL, "aud_l_sel", aud_l_parents,
H A Dclk-mt7988-topckgen.c176 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_L_SEL, "aud_l_sel", aud_l_parents, 0x070, 0x074, 0x078, 24,