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Searched refs:CLK_TOP_AUD_INTBUS_SEL (Results 1 – 24 of 24) sorted by relevance

/linux/include/dt-bindings/clock/
H A Dmt8135-clk.h78 #define CLK_TOP_AUD_INTBUS_SEL 67 macro
H A Dmt7629-clk.h100 #define CLK_TOP_AUD_INTBUS_SEL 90 macro
H A Dmt8516-clk.h168 #define CLK_TOP_AUD_INTBUS_SEL 136 macro
H A Dmt7622-clk.h85 #define CLK_TOP_AUD_INTBUS_SEL 73 macro
H A Dmediatek,mt6795-clk.h109 #define CLK_TOP_AUD_INTBUS_SEL 98 macro
H A Dmt8173-clk.h111 #define CLK_TOP_AUD_INTBUS_SEL 101 macro
H A Dmt6765-clk.h147 #define CLK_TOP_AUD_INTBUS_SEL 112 macro
H A Dmediatek,mt8365-clk.h87 #define CLK_TOP_AUD_INTBUS_SEL 77 macro
H A Dmt2712-clk.h148 #define CLK_TOP_AUD_INTBUS_SEL 117 macro
H A Dmt8192-clk.h40 #define CLK_TOP_AUD_INTBUS_SEL 28 macro
/linux/drivers/clk/mediatek/
H A Dclk-mt6795-topckgen.c479 TOP_MUX_GATE(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel", aud_intbus_parents,
H A Dclk-mt8173-topckgen.c563 MUX_GATE(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel", aud_intbus_parents,
H A Dclk-mt8135.c361 MUX_GATE(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel", aud_intbus_parents,
H A Dclk-mt7622.c428 MUX_GATE(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel", aud_intbus_parents,
H A Dclk-mt8516.c379 MUX(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel", aud_intbus_parents,
H A Dclk-mt7629.c500 MUX_GATE(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel", aud_intbus_parents,
H A Dclk-mt8167.c550 MUX(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel", aud_intbus_parents,
H A Dclk-mt2712.c674 MUX_GATE(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel", aud_intbus_parents,
H A Dclk-mt8365.c453 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel",
H A Dclk-mt8192.c615 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel",
H A Dclk-mt6765.c422 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel",
/linux/arch/arm64/boot/dts/mediatek/
H A Dmt8365.dtsi397 clocks = <&topckgen CLK_TOP_AUD_INTBUS_SEL>,
H A Dmt8192.dtsi511 clocks = <&topckgen CLK_TOP_AUD_INTBUS_SEL>,
1008 <&topckgen CLK_TOP_AUD_INTBUS_SEL>,
H A Dmt8173.dtsi868 <&topckgen CLK_TOP_AUD_INTBUS_SEL>,