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Searched refs:CLK_TOP_AUD_ENGEN2_SEL (Results 1 – 6 of 6) sorted by relevance

/linux/include/dt-bindings/clock/
H A Dmt8516-clk.h179 #define CLK_TOP_AUD_ENGEN2_SEL 147 macro
H A Dmediatek,mt8365-clk.h91 #define CLK_TOP_AUD_ENGEN2_SEL 81 macro
H A Dmt8192-clk.h56 #define CLK_TOP_AUD_ENGEN2_SEL 44 macro
/linux/drivers/clk/mediatek/
H A Dclk-mt8167.c590 MUX(CLK_TOP_AUD_ENGEN2_SEL, "aud_engen2_sel", aud_engen2_parents,
H A Dclk-mt8365.c465 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_ENGEN2_SEL, "aud_engen2_sel",
H A Dclk-mt8192.c651 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_ENGEN2_SEL, "aud_engen2_sel",