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Searched refs:CLK_TOP_AUD_2_SEL (Results 1 – 12 of 12) sorted by relevance

/linux/include/dt-bindings/clock/
H A Dmediatek,mt6795-clk.h117 #define CLK_TOP_AUD_2_SEL 106 macro
H A Dmt8173-clk.h120 #define CLK_TOP_AUD_2_SEL 110 macro
H A Dmediatek,mt8365-clk.h89 #define CLK_TOP_AUD_2_SEL 79 macro
H A Dmt2712-clk.h157 #define CLK_TOP_AUD_2_SEL 126 macro
H A Dmt8192-clk.h60 #define CLK_TOP_AUD_2_SEL 48 macro
/linux/drivers/clk/mediatek/
H A Dclk-mt6795-topckgen.c496 TOP_MUX_GATE(CLK_TOP_AUD_2_SEL, "aud_2_sel", aud_2_parents, 0xb0, 0, 2, 7, 0),
H A Dclk-mt8173-topckgen.c585 MUX_GATE(CLK_TOP_AUD_2_SEL, "aud_2_sel", aud_2_parents, 0x00b0, 0, 2, 7),
H A Dclk-mt2712.c688 MUX_GATE(CLK_TOP_AUD_2_SEL, "aud_2_sel", aud_2_parents, 0x0b0, 0, 2, 7),
H A Dclk-mt8365.c458 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_2_SEL, "aud_2_sel", aud_2_parents,
H A Dclk-mt8192.c660 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_2_SEL, "aud_2_sel",
/linux/arch/arm64/boot/dts/mediatek/
H A Dmt8173.dtsi887 <&topckgen CLK_TOP_AUD_2_SEL>;
H A Dmt8192.dtsi1012 <&topckgen CLK_TOP_AUD_2_SEL>,