Home
last modified time | relevance | path

Searched refs:CLK_TOP_AUD_1_SEL (Results 1 – 14 of 14) sorted by relevance

/linux/include/dt-bindings/clock/
H A Dmediatek,mt6795-clk.h116 #define CLK_TOP_AUD_1_SEL 105 macro
H A Dmt8173-clk.h119 #define CLK_TOP_AUD_1_SEL 109 macro
H A Dmt6765-clk.h148 #define CLK_TOP_AUD_1_SEL 113 macro
H A Dmediatek,mt8365-clk.h88 #define CLK_TOP_AUD_1_SEL 78 macro
H A Dmt2712-clk.h156 #define CLK_TOP_AUD_1_SEL 125 macro
H A Dmt8192-clk.h59 #define CLK_TOP_AUD_1_SEL 47 macro
/linux/drivers/clk/mediatek/
H A Dclk-mt6795-topckgen.c494 TOP_MUX_GATE(CLK_TOP_AUD_1_SEL, "aud_1_sel", aud_1_parents, 0xa0, 24, 2, 31, 0),
H A Dclk-mt8173-topckgen.c583 MUX_GATE(CLK_TOP_AUD_1_SEL, "aud_1_sel", aud_1_parents, 0x00a0, 24, 2, 31),
H A Dclk-mt2712.c686 MUX_GATE(CLK_TOP_AUD_1_SEL, "aud_1_sel", aud_1_parents, 0x0a0, 24, 2, 31),
H A Dclk-mt8365.c456 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_1_SEL, "aud_1_sel", aud_1_parents,
H A Dclk-mt8192.c658 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_1_SEL, "aud_1_sel",
H A Dclk-mt6765.c425 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_1_SEL, "aud_1_sel", aud_1_parents,
/linux/arch/arm64/boot/dts/mediatek/
H A Dmt8173.dtsi886 assigned-clocks = <&topckgen CLK_TOP_AUD_1_SEL>,
H A Dmt8192.dtsi1010 <&topckgen CLK_TOP_AUD_1_SEL>,