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Searched refs:CLK_TOP_AUDINTBUS_SEL (Results 1 – 4 of 4) sorted by relevance

/linux/include/dt-bindings/clock/
H A Dmediatek,mt6735-topckgen.h66 #define CLK_TOP_AUDINTBUS_SEL 58 macro
H A Dmt2701-clk.h99 #define CLK_TOP_AUDINTBUS_SEL 88 macro
/linux/drivers/clk/mediatek/
H A Dclk-mt6735-topckgen.c352 …MUX_GATE_CLR_SET_UPD(CLK_TOP_AUDINTBUS_SEL, "aud_intbus_sel", aud_intbus_sel_parents, CLK_CFG_4, C…
H A Dclk-mt2701.c520 MUX_GATE(CLK_TOP_AUDINTBUS_SEL, "aud_intbus_sel", aud_intbus_parents,