Searched refs:CLK_TOP_AUD2_SEL (Results 1 – 8 of 8) sorted by relevance
| /linux/include/dt-bindings/clock/ |
| H A D | mediatek,mt6735-topckgen.h | 74 #define CLK_TOP_AUD2_SEL 66 macro
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| H A D | mt7629-clk.h | 108 #define CLK_TOP_AUD2_SEL 98 macro
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| H A D | mt8516-clk.h | 177 #define CLK_TOP_AUD2_SEL 145 macro
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| H A D | mt7622-clk.h | 93 #define CLK_TOP_AUD2_SEL 81 macro
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| /linux/drivers/clk/mediatek/ |
| H A D | clk-mt6735-topckgen.c | 360 …MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD2_SEL, "aud_2_sel", aud_1_2_sel_parents, CLK_CFG_6, CLK_CFG_6_SET,…
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| H A D | clk-mt7622.c | 448 MUX_GATE(CLK_TOP_AUD2_SEL, "aud2_sel", aud2_parents,
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| H A D | clk-mt8167.c | 586 MUX(CLK_TOP_AUD2_SEL, "aud2_sel", aud2_parents,
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| /linux/arch/arm64/boot/dts/mediatek/ |
| H A D | mt7622.dtsi | 627 <&topckgen CLK_TOP_AUD2_SEL>,
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