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Searched refs:CLK_TOP_AUD2_SEL (Results 1 – 10 of 10) sorted by relevance

/linux/include/dt-bindings/clock/
H A Dmediatek,mt6735-topckgen.h74 #define CLK_TOP_AUD2_SEL 66 macro
H A Dmt7629-clk.h108 #define CLK_TOP_AUD2_SEL 98 macro
H A Dmt8516-clk.h177 #define CLK_TOP_AUD2_SEL 145 macro
H A Dmt7622-clk.h93 #define CLK_TOP_AUD2_SEL 81 macro
/linux/drivers/clk/mediatek/
H A Dclk-mt6735-topckgen.c360 …MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD2_SEL, "aud_2_sel", aud_1_2_sel_parents, CLK_CFG_6, CLK_CFG_6_SET,…
H A Dclk-mt7622.c448 MUX_GATE(CLK_TOP_AUD2_SEL, "aud2_sel", aud2_parents,
H A Dclk-mt8516.c397 MUX(CLK_TOP_AUD2_SEL, "aud2_sel", aud2_parents,
H A Dclk-mt7629.c518 MUX_GATE(CLK_TOP_AUD2_SEL, "aud2_sel", aud1_parents,
H A Dclk-mt8167.c586 MUX(CLK_TOP_AUD2_SEL, "aud2_sel", aud2_parents,
/linux/arch/arm64/boot/dts/mediatek/
H A Dmt7622.dtsi623 <&topckgen CLK_TOP_AUD2_SEL>,