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Searched refs:CLK_TOP_AUD1_SEL (Results 1 – 10 of 10) sorted by relevance

/linux/include/dt-bindings/clock/
H A Dmediatek,mt6735-topckgen.h73 #define CLK_TOP_AUD1_SEL 65 macro
H A Dmt7629-clk.h107 #define CLK_TOP_AUD1_SEL 97 macro
H A Dmt8516-clk.h176 #define CLK_TOP_AUD1_SEL 144 macro
H A Dmt7622-clk.h92 #define CLK_TOP_AUD1_SEL 80 macro
/linux/drivers/clk/mediatek/
H A Dclk-mt6735-topckgen.c359 …MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD1_SEL, "aud_1_sel", aud_1_2_sel_parents, CLK_CFG_6, CLK_CFG_6_SET,…
H A Dclk-mt7622.c446 MUX_GATE(CLK_TOP_AUD1_SEL, "aud1_sel", aud1_parents,
H A Dclk-mt8516.c395 MUX(CLK_TOP_AUD1_SEL, "aud1_sel", aud1_parents,
H A Dclk-mt7629.c516 MUX_GATE(CLK_TOP_AUD1_SEL, "aud1_sel", aud1_parents,
H A Dclk-mt8167.c584 MUX(CLK_TOP_AUD1_SEL, "aud1_sel", aud1_parents,
/linux/arch/arm64/boot/dts/mediatek/
H A Dmt7622.dtsi626 <&topckgen CLK_TOP_AUD1_SEL>,