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Searched refs:CLK_TOP_ATB_SEL (Results 1 – 16 of 16) sorted by relevance

/linux/include/dt-bindings/clock/
H A Dmediatek,mt6735-topckgen.h69 #define CLK_TOP_ATB_SEL 61 macro
H A Dmt7629-clk.h103 #define CLK_TOP_ATB_SEL 93 macro
H A Dmt7622-clk.h88 #define CLK_TOP_ATB_SEL 76 macro
H A Dmt8173-clk.h114 #define CLK_TOP_ATB_SEL 104 macro
H A Dmt6765-clk.h136 #define CLK_TOP_ATB_SEL 101 macro
H A Dmediatek,mt8365-clk.h76 #define CLK_TOP_ATB_SEL 66 macro
H A Dmt2712-clk.h151 #define CLK_TOP_ATB_SEL 120 macro
H A Dmt8192-clk.h42 #define CLK_TOP_ATB_SEL 30 macro
/linux/drivers/clk/mediatek/
H A Dclk-mt6735-topckgen.c355 …MUX_GATE_CLR_SET_UPD(CLK_TOP_ATB_SEL, "atb_sel", atb_sel_parents, CLK_CFG_5, CLK_CFG_5_SET, CLK_CF…
H A Dclk-mt8173-topckgen.c569 MUX_GATE(CLK_TOP_ATB_SEL, "atb_sel", atb_parents, 0x0090, 16, 2, 23),
H A Dclk-mt7622.c436 MUX_GATE(CLK_TOP_ATB_SEL, "atb_sel", atb_parents,
H A Dclk-mt7629.c507 MUX_GATE(CLK_TOP_ATB_SEL, "atb_sel", atb_parents,
H A Dclk-mt2712.c680 MUX_GATE(CLK_TOP_ATB_SEL, "atb_sel", atb_parents, 0x090, 16, 2, 23),
H A Dclk-mt8365.c422 MUX_GATE_CLR_SET_UPD(CLK_TOP_ATB_SEL, "atb_sel", atb_parents, 0x050,
H A Dclk-mt8192.c619 MUX_GATE_CLR_SET_UPD(CLK_TOP_ATB_SEL, "atb_sel",
H A Dclk-mt6765.c386 MUX_GATE_CLR_SET_UPD(CLK_TOP_ATB_SEL, "atb_sel", atb_parents, CLK_CFG_1,