Searched refs:CLK_TOP_APLL1_DIV5 (Results 1 – 4 of 4) sorted by relevance
| /linux/include/dt-bindings/clock/ |
| H A D | mediatek,mt6795-clk.h | 131 #define CLK_TOP_APLL1_DIV5 120 macro
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| H A D | mt8173-clk.h | 136 #define CLK_TOP_APLL1_DIV5 126 macro
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| /linux/drivers/clk/mediatek/ |
| H A D | clk-mt6795-topckgen.c | 516 DIV_GATE(CLK_TOP_APLL1_DIV5, "apll1_div5", "apll1_div4", 0x12c, 13, 0x12c, 4, 0),
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| H A D | clk-mt8173-topckgen.c | 611 DIV_GATE(CLK_TOP_APLL1_DIV5, "apll1_div5", "apll1_div4", 0x12c, 13, 0x12c, 4, 0),
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