Searched refs:CLK_TOP_APLL1_DIV4 (Results 1 – 4 of 4) sorted by relevance
| /linux/include/dt-bindings/clock/ |
| H A D | mediatek,mt6795-clk.h | 130 #define CLK_TOP_APLL1_DIV4 119 macro
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| H A D | mt8173-clk.h | 135 #define CLK_TOP_APLL1_DIV4 125 macro
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| /linux/drivers/clk/mediatek/ |
| H A D | clk-mt6795-topckgen.c | 515 DIV_GATE(CLK_TOP_APLL1_DIV4, "apll1_div4", "aud_1_sel", 0x12c, 12, 0x124, 8, 24),
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| H A D | clk-mt8173-topckgen.c | 610 DIV_GATE(CLK_TOP_APLL1_DIV4, "apll1_div4", "aud_1_sel", 0x12c, 12, 0x124, 8, 24),
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