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Searched refs:CLK_TOP_APLL12_CK_DIV9 (Results 1 – 2 of 2) sorted by relevance

/linux/include/dt-bindings/clock/
H A Dmediatek,mt8188-clk.h195 #define CLK_TOP_APLL12_CK_DIV9 184 macro
/linux/drivers/clk/mediatek/
H A Dclk-mt8188-topckgen.c1187 DIV_GATE(CLK_TOP_APLL12_CK_DIV9, "apll12_div9", "top_dptx", 0x0320, 9, 0x0338, 8, 8),