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Searched refs:CLK_TOP_APLL12_CK_DIV4 (Results 1 – 11 of 11) sorted by relevance

/linux/include/dt-bindings/clock/
H A Dmt8516-clk.h200 #define CLK_TOP_APLL12_CK_DIV4 168 macro
H A Dmediatek,mt8365-clk.h126 #define CLK_TOP_APLL12_CK_DIV4 116 macro
H A Dmt8186-clk.h153 #define CLK_TOP_APLL12_CK_DIV4 134 macro
H A Dmediatek,mt8188-clk.h194 #define CLK_TOP_APLL12_CK_DIV4 183 macro
/linux/drivers/clk/mediatek/
H A Dclk-mt8186-topckgen.c678 DIV_GATE(CLK_TOP_APLL12_CK_DIV4, "apll12_div4", "apll_i2s4_mck_sel",
H A Dclk-mt8516.c487 DIV_ADJ(CLK_TOP_APLL12_CK_DIV4, "apll12_ck_div4", "aud_i2s4_m_sel",
H A Dclk-mt8167.c676 DIV_ADJ(CLK_TOP_APLL12_CK_DIV4, "apll12_ck_div4", "aud_i2s4_m_sel",
H A Dclk-mt8365.c561 DIV_ADJ_F(CLK_TOP_APLL12_CK_DIV4, "apll12_ck_div4", "apll_tdmout_sel",
H A Dclk-mt8188-topckgen.c1189 DIV_GATE(CLK_TOP_APLL12_CK_DIV4, "apll12_div4", "top_aud_iec", 0x0320, 4, 0x0334, 8, 0),
/linux/arch/arm64/boot/dts/mediatek/
H A Dmt8186.dtsi1526 <&topckgen CLK_TOP_APLL12_CK_DIV4>,
H A Dmt8188.dtsi1416 <&topckgen CLK_TOP_APLL12_CK_DIV4>,