Searched refs:CLK_TOP_APLL12_CK_DIV4 (Results 1 – 7 of 7) sorted by relevance
| /linux/include/dt-bindings/clock/ |
| H A D | mt8516-clk.h | 200 #define CLK_TOP_APLL12_CK_DIV4 168 macro
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| H A D | mediatek,mt8365-clk.h | 126 #define CLK_TOP_APLL12_CK_DIV4 116 macro
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| H A D | mt8186-clk.h | 153 #define CLK_TOP_APLL12_CK_DIV4 134 macro
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| /linux/drivers/clk/mediatek/ |
| H A D | clk-mt8186-topckgen.c | 678 DIV_GATE(CLK_TOP_APLL12_CK_DIV4, "apll12_div4", "apll_i2s4_mck_sel",
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| H A D | clk-mt8167.c | 676 DIV_ADJ(CLK_TOP_APLL12_CK_DIV4, "apll12_ck_div4", "aud_i2s4_m_sel",
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| H A D | clk-mt8365.c | 561 DIV_ADJ_F(CLK_TOP_APLL12_CK_DIV4, "apll12_ck_div4", "apll_tdmout_sel",
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| H A D | clk-mt8188-topckgen.c | 1189 DIV_GATE(CLK_TOP_APLL12_CK_DIV4, "apll12_div4", "top_aud_iec", 0x0320, 4, 0x0334, 8, 0),
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