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Searched refs:CLK_TOP_APLL12_CK_DIV2 (Results 1 – 9 of 9) sorted by relevance

/linux/include/dt-bindings/clock/
H A Dmt8516-clk.h198 #define CLK_TOP_APLL12_CK_DIV2 166 macro
H A Dmediatek,mt8365-clk.h124 #define CLK_TOP_APLL12_CK_DIV2 114 macro
H A Dmt8186-clk.h152 #define CLK_TOP_APLL12_CK_DIV2 133 macro
H A Dmediatek,mt8188-clk.h192 #define CLK_TOP_APLL12_CK_DIV2 181 macro
/linux/drivers/clk/mediatek/
H A Dclk-mt8186-topckgen.c676 DIV_GATE(CLK_TOP_APLL12_CK_DIV2, "apll12_div2", "apll_i2s2_mck_sel",
H A Dclk-mt8516.c483 DIV_ADJ(CLK_TOP_APLL12_CK_DIV2, "apll12_ck_div2", "aud_i2s2_m_sel",
H A Dclk-mt8167.c672 DIV_ADJ(CLK_TOP_APLL12_CK_DIV2, "apll12_ck_div2", "aud_i2s2_m_sel",
H A Dclk-mt8365.c557 DIV_ADJ_F(CLK_TOP_APLL12_CK_DIV2, "apll12_ck_div2", "apll_i2s2_sel",
H A Dclk-mt8188-topckgen.c1187 DIV_GATE(CLK_TOP_APLL12_CK_DIV2, "apll12_div2", "top_i2so1", 0x0320, 2, 0x0328, 8, 16),