Searched refs:CLK_TOP2_SENINF0 (Results 1 – 2 of 2) sorted by relevance
417 MUX_GATE_HWV_FENC_CLR_SET_UPD(CLK_TOP2_SENINF0, "seninf0", seninf_parents,
155 #define CLK_TOP2_SENINF0 0 macro